Wafer Level

In opto-electronic device manufacturing, wafer level refers to the stage of fabrication of Integrated Circuits where the individual devices are still bound together on a “slice” of semiconductor material. Wafer level packaging is used in packaging of integrated circuits. Wafer level packaging is a chip-scale package technology. The reason is that the resulting package is practically of the same size as the die.

In contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them, Wafer level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer. Wafer level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment. There are no industrial standard methods for wafer level packaging to this writing.